In the integrated circuit (IC), i.e. chip, fabrication technique, the working voltage of function circuits in a chip has become lower than before, that is, nowadays chips have lower capacity for bearing noises than before. Furthermore, the area of electronic component has also become smaller. Therefore, a quantity of function circuits disposed in a chip has increased, which requires higher current density. On the other hand, a three dimensional integrated circuit (3DIC), i.e. 3D chip has been developed to allow more function circuits to be arranged within different layers. Because of arranging these function circuits within different layers, the distance between power lines in the 3D chip will become longer than that in a 2D chip (2DIC), resulting in higher resistance effect which causes relative voltage drop when a power line powers a function circuit.
Generally, it may increase the decoupling capacitance value of the function circuit or use a power layout design in the layout of chip to compensate such a power drop. However, the power layout design may have the voltage attenuation effect caused by different loads of the function circuit in different working conditions, and the means of increasing the decoupling capacitance value in the function circuit may use an unsuitable capacitance because of considering the suitable response time of the function circuit.